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NXP Semiconductors /QN908XC /SPI0 /INTENCLR

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Interpret as INTENCLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SSAEN)SSAEN 0 (SSDEN)SSDEN 0 (MSTIDLE)MSTIDLE

Description

SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.

Fields

SSAEN

Writing 1 clears the corresponding bit in the INTENSET register.
SSDEN

Writing 1 clears the corresponding bit in the INTENSET register.
MSTIDLE

Writing 1 clears the corresponding bit in the INTENSET register.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data